Flash memory devices are widely used non-volatile memory devices that can electrically erase or rewrite data. Flash memory devices may consume less power than magnetic disc memory-based storage media and may have a fast access time like hard discs.
Flash memory devices may be classified into NOR flash memory devices and NAND flash memory devices according to a connection structure of cells and bit lines. NOR flash memory devices generally have one bit line and two or more cell transistors connected in parallel, store data by using a channel hot electron method, and erase data by using a Fowler-Nordheim (F-N) method. NAND flash memory devices generally have one bit line and two or more cell transistors connected in series, and store and erase data by using an F-N tunneling method. In general, NOR flash memory devices may have relatively high current consumption, but may have an advantage of high speed operation. NAND flash memory devices may allow high integration because of generally lower cell current consumption than NOR flash memory devices.
FIG. 1 is a cross-sectional view illustrating a conventional unit cell of a flash memory device.
Referring to FIG. 1, the flash memory device stores data in an array of floating gate transistors called cells. In detail, the flash memory device may include a p-type semiconductor substrate 11 doped with boron ions or the like. An n-type source region 12 and an n-type drain region 13 may be formed by doping phosphorus, arsenic, antimony and/or the like into the substrate 11. A floating gate 14 may be formed over the substrate 11, and may be isolated from the substrate 11. A control gate 15 may be formed over the floating gate 14, and may be isolated from the floating gate 14. Since the floating gate 14 is isolated, charges stored in the floating gate 14 are trapped and data can be retained in the floating gate 14 without significant power consumption.
FIG. 2A is a circuit diagram illustrating memory cells included in a conventional NAND flash memory device.
Referring to FIG. 2A, the conventional NAND flash memory device includes a plurality of word lines WL11 through WL14 and a plurality of memory cells M11 through M14. The memory cells M11 through M14 form a string structure together with select transistors ST1 and ST2 and are connected in series between a bit line BL and a ground voltage terminal VSS. Since the conventional NAND flash memory device can use small cell current, the memory cells connected to one word line can be programmed by a one-time program operation.
FIG. 2B is a circuit diagram illustrating memory cells included in a conventional NOR flash memory device.
Referring to FIG. 2B, the conventional NOR flash memory device includes a plurality of memory cells M21 through M26 connected to bit lines BL1 and BL2 and a source line CSL. Since the conventional NOR flash memory device can use large cell current, a predetermined number of memory cells may be programmed by a one-time program operation.
FIGS. 3A and 3C are graphs illustrating cell threshold voltages of stored data when memory cells of a flash memory device are single-level memory cells. FIGS. 3B and 3D are graphs illustrating cell threshold voltages of stored data when memory cells of a flash memory device are multi-level memory cells.
Referring to FIGS. 3A and 3C, 1-bit data is stored with two different threshold voltages that are programmed in the single-level memory cell. For example, in the case of FIG. 3A, when a threshold voltage programmed in the single-level memory cell ranges 1 through 3V, data stored in the single-level memory cell is logic “1”. When a threshold voltage programmed in the single-level memory cell ranges from 5 to 7V, data stored in the single-level memory cell is logic “0”. FIG. 3A illustrates a voltage distribution of a single-level cell NOR flash memory device. FIG. 3C illustrates a voltage distribution of a single-level cell NAND flash memory device.
Referring to FIGS. 3B and 3D, 2-bit data is stored with 4 different threshold voltages that are programmed in the multi-level memory cell. For example, when a threshold voltage programmed in the multi-level memory cell ranges from 1 to 3V, data stored in the multi-level memory cell is logic “11”. When a threshold voltage programmed in the multi-level memory cell ranges from 3.8 to 4.2V, data stored in the multi-level memory cell is logic “10”. When a threshold voltage programmed in the multi-level memory cell ranges from 4.9 to 5.4V, data stored in the multi-level memory cell is logic “01”. When a threshold voltage programmed in the multi-level memory cell ranges from 6.5 to 7.0V, data stored in the multi-level memory cell is logic “00”. FIG. 3B illustrates a voltage distribution of a multi-level cell NOR flash memory device. FIG. 3D illustrates a voltage distribution of a multi-level cell NAND flash memory device.
Data stored in a single-level or multi-level memory cell of the flash memory device is identified according to a difference in cell current during a data read operation. The operations and types of the conventional flash memory devices described above are well known to one of ordinary skill in the art, and thus a detailed explanation thereof need not be given.
Flash memory devices use not only program voltages of various levels, but also use high voltages of various levels such as read voltages, pass voltages, and erase voltages. In general, flash memory devices include a high voltage generating circuit in order to generate high voltages of various levels. Since a margin between voltages in the flash memory devices may be small, it may be desirable to generate a high voltage of an accurate level. For example, when multi-level cell flash memory devices perform a program operation by using an increment step plus program (ISPP) method, step voltages with a smaller margin may be used and, thus, it may be further desirable to generate a voltage of an accurate level. Accordingly, flash memory devices generally include a circuit for measuring a high voltage and checking whether the high voltage has an accurate level.
FIG. 4 is a block diagram of a conventional circuit 40 for measuring a high voltage.
Referring to FIG. 4, the conventional circuit 40 includes a plurality of switch units 40_1 through 40_n. The switch units 40_1 through 40_n receive input high voltages of different levels. When corresponding enable signals are activated, the switch units 40_1 through 40_n apply corresponding input high voltages to corresponding high voltage measurement pads.
For example, the first switch unit 40_1 receives a first input high voltage HV1 of a first level, and the second switch unit 40_2 receives a second input high voltage HV2 of a second level. Likewise, the nth switch unit 40_n receives an nth input high voltage HVn of an nth level. When a first enable signal EN1 is activated, the first switch unit 40_1 outputs the first input high voltage HV1 to a first high voltage measurement pad MPAD1. Next, a measurement unit (not shown) measures the voltage of the first high voltage measurement pad MPAD1, and measures the voltage level of the first input high voltage HV1. The second through nth switch units 40_2 through 40_n operate in the same manner.
When the switch units of FIG. 4 apply corresponding input high voltages to measurement pads in response to corresponding enable signals, transistors are used as switches. Accordingly, in order to measure a given high voltage, a high voltage that exceeds the given high voltage by at least a threshold voltage should be applied to a gate of a transistor. That is, in order to measure one high voltage, another separate high voltage may need to be generated and also may need to be measured. Furthermore, in order to measure high voltages of different levels, the conventional circuit 40 should include measurement pads corresponding to the high voltages of different levels.